Shallow trench isolation (STI) structures are formed in a substrate to electrically isolate regions of adjacent semiconductor devices that are formed in the substrate. Each STI structure includes oxide (STI oxide), and each STI structure has a corresponding STI step height. The step height of a STI structure is the distance, in a vertical dimension, from a lateral surface of the STI structure to a lateral surface of a gate stack. Specifically, the lateral surface of the gate stack that is of interest, when determining the step height of the STI structure, is the lateral surface of the gate stack that is directly on the substrate. Moreover, the lateral surface of the STI structure that is of interest, when determining the step height of the STI structure, is the lateral surface of the STI structure that is closest in distance, in the vertical dimension, to the lateral surface of the gate stack. The lateral surface of the gate stack is parallel to the lateral surface of the STI structure. In addition, the STI step height corresponding to each STI structure depends on the amount of STI oxide loss caused by a pre-gate oxidation cleaning process, wherein the pre-gate oxidation cleaning process includes performing one or more hydrofluoric (HF) wet etch steps that can remove an amount of STI oxide. Each STI structure may have different doping profiles that can cause the STI oxide of more than one STI structure to be etched at different rates. Moreover, having more than one STI structure etched at different rates can cause STI step height to vary thereby resulting in systematic STI step height variation that adds to general process variation when fabricating semiconductor integrated circuits (ICs). The STI step height variation and general process variation can reduce yield rates of a semiconductor fabrication system for creating ICs with STI structures.
Yield rate refers to the percentage of usable ICs produced by the semiconductor fabrication system compared to the total number of usable ICs attempted by the semiconductor fabrication system. Also, yield rate may refer to the percentage of usable ICs obtained on average from a semiconductor wafer that is processed through the semiconductor fabrication system. Low yield rates may be caused by defects from foreign material, semiconductor structures formed with a lack of process margin, and/or lack of process variation control by the semiconductor fabrication system that creates the ICs.
A common defect is a precursor defect that can cause formation of voids in a dielectric layer of the ICs. The formation of voids in the dielectric layer can occur by having higher gap fill aspect ratios than a semiconductor fabrication system process is capable of handling, wherein the dielectric layer is formed on an STI structure of the ICs. Moreover, the formation of voids and the size of the voids in the dielectric layer can increase due to variation in STI step height. In addition, during subsequent processing after forming of the dielectric layer the voids may become exposed by chemical-mechanical planarization (CMP) and filled with conductive material creating a conductive stringer. The conductive stringer is a defect that may become a region of abnormally low electrical impedance, which can result in a short circuit and decrease yield rate. Thus, variation in STI step height can cause defects in the ICs, such as void formation and conductive stringers that present difficulties in achieving high yield rates for the semiconductor fabrication system.